1. Field of the Invention
The present invention relates to a semiconductor memory device adapted to an ECC (Error Checking and Correcting) function, and more particularly to a semiconductor memory device in which a memory bus width can be reduced, as well as a controller controlling the same.
2. Description of the Background Art
Recently, a processing speed of a computer has remarkably been enhanced, and accordingly, a function to improve reliability of the computer has been required. The ECC function is one example of such function. In the computer of which high reliability is demanded, a memory device adapted to the ECC function is employed as a main memory in many cases. Therefore, even if an error occurs, the error can be corrected using parity data.
For example, if 8-bit parity data is added to original data of 64 bits, an error of arbitrary 1 bit among 72 bits can be corrected, and an error of 2 or more bits can be detected.
An invention disclosed in Japanese Patent Laying-Open No. 11-65944 relates to such technology. A data error detecting circuit disclosed in Japanese Patent Laying-Open No. 11-65944 includes k ECC circuits with a function to detect n-bit burst error, and is configured such that m-bit data output from each memory element is divided into k pieces, which are in turn input to separate, k ECC circuits. In this manner, even if the number of output bits of the memory element constituting a memory device increases, a defect that occurred in the memory element can be detected by means of the ECC circuit which is used when the number of output bits of the memory element is small.
On the other hand, though the data error detecting circuit disclosed in Japanese Patent Laying-Open No. 11-65944 described above can adapt to an increase in the number of output bits of the memory element, the memory bus width itself cannot be reduced. That is, if the ECC function is added to the system, the memory bus width is increased. Therefore, it is difficult to add the ECC function to a compact system.